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A COMPARATIVE ANALYSIS OF DIFFERENT CMOS LOGIC DESIGN TECHNIQUES FOR LOW POWER AND HIGH SPEED

Sandeep Sangwan, Mrs. Jyoti Kedia, Deepak Kedia

In this paper the comparative analysis of various CMOS logic design techniques for various important constraints such as power, area and speed has been done. The logic design techniques considered are Static CMOS, Domino logic, Feedthrough Logic (FTL), Modified FTL and Zigzag Keeper. Static CMOS dissipates less power but it uses more number of PMOS transistors resulting in large area and in some cases (when PMOS are in series) results in large delay. Domino logic improves the speed of the circuit and reduces area but at the cost of large power dissipation. Feedthrough logic which is the improved version of dynamic logic family further improves the speed of the circuits but it also dissipates more power. The modified FTL largely improves the power consumption of FTL logic but delay increases. Zigzag Keeper technique highly improves the power consumption but area is highly increased. At last a qualitative and quantitative analysis has been shown between different techniques for power and delay.