Abstrait

Design & Implementation of Nios II Processor for Low Powered Embedded Systems

R. BalaKumar, S. Kalimuthukumar

The purpose of the paper is to reduce memory and power of an embedded system. In earlier, embedded processors to perform the task whereas power and energy constraints should be lower. There are several tools available for improving the power and energy for low level processors. With the evolution of technology, the system complexity get increased and the application fields of the embedded system expanded. The need of high performance applications has led to the development of System on Chip (SoC). This paper presents the design of SoC (System on Chip) for the required hardware. Analyze the energy and power for the design in Quartus II. The evolution of technologies is enabling to the integration of complex platforms in a single chip (called system-on-chip, SoC) including one or several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. The Hardware level design is to be done in the Quartus II and Qsys. The design of SoC is to be done in the Qsys System Integration for the VGA display. The power tool to obtain power/energy estimation of complete system of SoC. The power / energy accuracy trade-offs for the SoC is to be measured. Then analyse the power and energy measures using power analyzer tool. Reduce the unnecessary logic and reduce memory access. It will reduces the power usage in the application. The usefulness and the effectiveness of the proposed system is achieved by using FPGA cyclone board with the help of Computer Aided Design Tools. The CAD tools are Quartus Altera II, Qsys, and Nios IDE Eclipse.