Abstrait

Design of Positive Edge Triggered D Flip-Flop Using 32nm CMOS Technology

Prathamesh G. Dhoble, Avinash D. Kale

The usage of the low power consumptions devices in today’s global village has become pervasive and indispensable in almost every walk of life. The thrust is towards reducing the high power energy consumption, required to reduce cost of the circuitry, while increasing the speed of performances in any operations. A high speed low power consumption positive edge triggered Delayed (D) flip-flop can be design for increasing the speed of counter in Phase locked loop, using 32 nm CMOS technology. Here we design D flip-flop for Phase locked loop (PLL). Phase locked loop is an important analog circuit used in various communication applications such as frequency synthesizer, radio computer, clock generation microprocessors etc. The design counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will faster than conventional circuit as it will have fast reset operation. The circuit will consumes less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply. The CMOS based fast D flip-flop circuit can be design and simulated by using Microwind 3.1 tool.