Abstrait

Design of Reliable Custom Topology for Application Specific Network-On-Chip

Dr. M. Maheswari

In this paper, Reliable custom topology for Application Specific Network-on-Chip (ASNoC) which consumes less area and power consumption with high data protection (error free) is proposed. The proposed design is achieved in two steps. First a custom topology is designed for ASNoC. Second, to improve the reliability of the custom topology, three novel error correction mechanisms have been designed and incorporated in the custom topology. The proposed three error correction codes consume less are and power consumption with high error correction capability compared to the existing error correction codes. Finally the proposed error correction codes are embedded in the custom topology to generate reliable custom topology. Cadence RTL encounter tool has been used for the analysis. The generated custom topology achieves 90% & 40% reliability improvement on data through on chip inter connects in low noise and in high noise environment respectively.