Abstrait

Implementation of Scheduling Tasks between different processing elements in a Network-On-chip

J.Senthil Kumar, P.K.SaranyaDevi

Scheduling of tasks between various processors in a Network-on-Chip is a challenging job. Interconnection of various processing elements with guaranteed traffic permutation and optimality of Scheduling over the Network-On-Chip has been reported in this paper. It supports to reduce the complexity of on chip network implementation. The proposed network topology contains a dynamic probing mechanism to interconnect different processing elements to make a path setup dynamically by using the probe routing algorithm, multistage network topology and communication locality on Network-on-Chip were implemented with reduced area constraints on chip. The communication locality on chip, using an optimized routing algorithm with 8 processing elements communicate over the Network-On-Chip, it provides guaranteed traffic throughput and perfect scheduling. The implementation of scheduling and the proposed network-on-chip also results in reduced number of switches, reduced Cost, improves bandwidth usage, and improves average path length usage with better passable Permutation. It also provides better strategy for scheduling of tasks between various processing elements in the on chip network.