Abstrait

Radix 25 FFT Architecture Implementation in Xilinx FPGA

S.Selvakumar, L.Stephy jasmine rani, G.Vijayalakshmi, N.Vishnudevi,N.Janakiraman

FFT is a highly efficient procedure to reduce computation time and also improves the performance. The Radix 22, 23 and 24 FFT architectures are not efficient because of its low utilization of components. Our proposed design will provide high data throughput and low complexity VLSI structure for Radix 25 FFT architecture. Most of previous architectures were designed using the complex booth multipliers, but our proposed architecture uses canonical signed digit (CSD) multiplier circuit. This entire proposed architecture simulated in Xilinx 12.2 system edition software and implemented in Xilinx Virtex-5 XUP FPGA kit. To optimize the power, area and speed of the signal process, pipelining and parallel processing techniques have to be used in this proposal. In future this Radix 25 FFT architecture will be incorporated in MIMO-OFDMA based software defined radio (SDR) architecture