Abstrait

Study, Simulation and Analysis of Advanced Encryption Standard (AES) Algorithm

B.Sujitha, Dr.B.Karthikeyan

The aim of this project is to attain an encrypted pre configured logic function for FPGA.Such a function should have a security values such as resistant to Differential Power Analysis (DPA) Attacks and it should also be free from cloning or duplication.AES-Rijndael Algorithm which is a block Cipher is used for encryption in some of cryptographic devices such as smart cards, RFIDs can be attacked with the help of the amount of data. The FPGA is processing and the operation it performs over those data by measuring the time taken for the process and also the power consumed during the process. This cryptanalytic technique is called as Side Channel Attacks (SCA).Among such attacks we are focussing on the power consumed by the process and terming it as Differential Power Analysis (DPA) attack.Here our objective is to take preventive steps to make our data and its operation independent of power it consumes such that possibility of DPA attacks can be greatly reduced. Further, The Secure Hashing Algorithm is applied in to an AES, it takes an arbitrary bit string as input and returns a fixed length string as output. The hash value is nearly impossible to derive the original input number without knowing the data used to create the hash value.